Up to now, as a solid-state image pickup element, a CMOS (Complementary Metal Oxide Semiconductor) type image sensor is known. As the CMOS image sensor is fabricated on a base of a CMOS LSI manufacturing process, it is possible to easily incorporate a function other the image sensor in the same chip through an application of this process. By utilizing this characteristic, an analog digital converter (which will be hereinafter referred to as ADC) is provided for each column of pixels, and a conduct of a conversion processing into a digital signal is performed in parallel in the respective columns. This system is referred to as column ADC system.
FIG. 1 shows a configuration example of a solid-state image pickup element for performing an A/D (Analog/Digital) conversion through the column ADC system. This solid-state image pickup element 100 has a pixel array unit 20 composed by arranging pixels 210 in m columns lengthwise and n rows crosswise in a matrix manner, a row scanning circuit 30, a column scanning circuit 40, and a timing control circuit 50.
Also, the solid-state image pickup element 100 is provided with an ADC 60-0 to an ADC 60-m provided while corresponding to the respective columns in the pixel array unit 20 and a reference signal generation unit 70 for supplying a reference voltage RAMP for the A/D conversion to the ADC 60-0 to the ADC 60-m. The ADC 60-0 to the ADC 60-m are respectively provided with a comparator (REF) 601-0 to a comparator 601-m and a latch unit 602-0 to a latch unit 602-m.
The solid-state image pickup element 100 further has a sense amplifier 80 and a capturing unit 90. It should be noted that in FIG. 1, although only the latch unit 602-0 to the latch unit 602-m are illustrated only in one row, but in actuality, it is supposed that these are lined up and arranged in a column direction by the number of output bits (10 bits, 12 bits, or the like). To elaborate, while corresponding to these, a plurality of pairs of the sense amplifier 80 and the capturing unit 90 are also arranged.
The respective pixels 210 in the pixel array unit 20 are connected to row selection lines Hi and column selection lines Vj (i and j are both natural numbers). The row scanning circuit 30 selects the row selection line Hi where read of a pixel value is desired to be performed among the row selection lines H0 to Hn. The column scanning circuit 40 selects the column selection line Vj where a pixel value is desired to be read in the row selection line Hi selected by the row scanning circuit 30. The timing control circuit 50 generates an internal clock on the basis of an input control clock to be output to the row scanning circuit 30, the column scanning circuit 40, the ADC 60-0 to the ADC 60-m, the reference signal generation unit 70, and the like.
It should be noted that in the following description, in a case where it is not necessary to respectively individually distinguish the ADC 60-0 to the ADC 60-m from each other, these are simply referred to as ADC 60, and in a case where it is not necessary to individually distinguish the comparator (REF) 601-0 to the comparator 601-m from each other, these are simply referred to as comparator 601. Furthermore, in a case where it is not necessary to individually distinguish the latch unit 602-0 to the latch unit 602-m from each other, these are simply referred to as latch unit 602.
The comparator 601 of the ADC 60 compares the reference voltage RAMP input from the reference signal generation unit 70 with an output value of the pixel 210 transmitted through the column selection line Vj and performs an output by inverting a phase of the output signal when the magnitudes of the reference voltage RAMP and the output value of the pixel 210 are matched with each other.
The latch unit 602 continuously counts the number of clocks until the output of the comparator 610 is changed and holds a digital count value in accordance with a comparison period when the output of the comparator 610 is changed. The count value held by the latch unit 602 is scanned by the column scanning circuit 40 and sequentially extracted by two-phase bus lines B10 and B20. The count values extracted by the two-phase bus lines B10 and B20 exist as differential signals whose phases are mutually inverse.
The sense amplifier 80 functioning as an amplification unit amplifies the differential signals input through the bus line B10 and the bus B20 to be output to the capturing unit 90. The capturing unit 90 is composed, for example, of a flip-flop circuit and latches the output from the sense amplifier 80 in synchronism with a supplied control clock. The value (pixel value) latched by the sense amplifier 80 is output to an output data processing circuit which is not shown in the drawing in synchronism with the control clock.
Incidentally, in the solid-state image pickup element 100 shown in FIG. 1, because of a difference in physical distances from a plurality of latch unit 602 to the sense amplifier 80, a problem occurs in which a deviation is generated in the data capturing timings in the sense amplifier 80. To elaborate, a time until the signal of the pixel value is supplied from the respective latch units 602 lined up and arranged by the number of pixels in the column direction to the sense amplifier 80 depends on distances of the bus lines B10 and B20 where the signal is transmitted. For this reason, a difference is generated between a timing for capturing output data from the latch unit 602-m located at a position closest from the sense amplifier 80 (near end) and a timing for capturing output data from the latch unit 602-0 located at a position farthest from the sense amplifier (far end).
When the data is latched by the capturing unit 90, a hold time is tight with respect to the data at the near end, and a set up time is tight with respect to the data at the far end. For this reason, depending on a magnitude of the deviation in the capturing timings because of the far and near end differences, the data may be captured out of synchronization by one pixel.
Also, there is a possibility that a difference may be generated in a time for the data to be transmitted through the bus line B10 and the bus line B20 depending on a variation at the time of a process of a semiconductor chip constituting this circuit. Up to now, a capturing period is uniformly set without taking such variation into account, and thus, both the data output from the far end and the data output from the near end cannot be captured within a predetermined period in some cases.
Furthermore, the time for the data to be transmitted through the bus line B10 and the bus line B20 also depends on a fluctuation of a power supply voltage and a change in temperature. Also, in recent years, realization of a higher definition of an image and a faster frame rate is advanced, and along with this, a time allowed to capture data on one pixel is being shortened. To elaborate, an allowable amount with respect to the deviation in the data capturing timings by the sense amplifier 80 is also being narrowed.
The capturing timing can also be adjusted by changing a mask, and according to this, it is possible to set different values for each chip. However, it takes considerable labor hours to perform these, and it is conceivable that the execution is difficult.
The present invention has been made in view of the above-mentioned points, and it is an object to make it possible to appropriately set the capturing timing for the pixel value.